SH7280 Datasheet, PDF (1641/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 31 Electrical Characteristics
Th
T1
Twx
T2
Tf
CK
t_AD1
t_AD1
A25 to A0
t_CSD1
t_CSD1
CSn
WEn
t_RWD1
t_WED1
t_WED1
t_RWD1
RD/WR
Read
RD
D31 to D0
tRSD
t_RSD
t_RDS1
t_RDH1
Write
RD/WR
tRWD1
t_WDD1
t_RWD1
t_WDH1
D31 to D0
BS
DACKn
TENDn*
t_BSD
t_DACD
t_BSD
t_WTH
t_WTH
t_DACD
WAIT
t_WTS
tWTS
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.16 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle,
One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))
Rev. 1.00 Jun. 26, 2008 Page 1611 of 1692
REJ09B0393-0100