SH7280 Datasheet, PDF (1029/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
Table 20.6 A/D Conversion Time
Item
Symbol Min.
A/D conversion start delay time
t_D
11*¹
Analog input sampling time of sample- t_SPLSH
—
and-hold circuits dedicated to GrA
Offset canceling processing time
t
—
OFC
Analog input sampling time of sample- t
—
SPL
and-hold circuit common to all channels
Completion of conversion
t_end
A/D
ADBYPSCR.SH = 0,
t
CONV
conversion ADBYPSCR.OFC = 0
time
ADBYPSCR.SH = 0,
ADBYPSCR.OFC = 1
—
50n + 65*³
50n + 15*³
ADBYPSCR.SH = 1,
ADBYPSCR.OFC = 0
50n + 95*³
ADBYPSCR.SH = 1,
ADBYPSCR.OFC = 1
50n + 45*³
Notes: 1. A/D activation by MTU2, MTU2S trigger signal
2. A/D activation by the external trigger signal
3. n is a number of channel (n = 1 to 4)
Typ.
—
30
50
20
4
—
—
—
—
Max.
15*²
—
—
—
—
50n + 69*³
50n + 19*³
50n + 99*³
50n + 49*³
TRGAN
(MTU2, MTU2S trigger signal)
ADST
tD
Sampling and
hold time (tSPLSH)*¹
A/D conversion time (tCONV)
tOFC*²
Sampling and
hold time (tSPL)
Conversion complete
processing (tend)
A/D
converter
ADDR
Waiting
Sample-
and-hold
OFC
Sample-
and-hold
A/D
conversion
ADF
Notes: *1 tSPLSH can be reduced by clearing the SH bit in ADBYPSCR to 0.
*2 tOFC can be reduced by setting the OFC bit in ADBYPSCR to 1.
Conversion time
per channel
50 states
(Aφ = 50 MHz: 1.00 µs)
Figure 20.10 A/D Conversion Timing
Waiting
End of A/D
conversion
Rev. 1.00 Jun. 26, 2008 Page 999 of 1692
REJ09B0393-0100