SH7280 Datasheet, PDF (13/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

7.3.13 Break Control Register (BRCR) ....................................................................... 185
7.4 Operation .......................................................................................................................... 189
7.4.1 Flow of the User Break Operation .................................................................... 189
7.4.2 Break on Instruction Fetch Cycle...................................................................... 190
7.4.3 Break on Data Access Cycle............................................................................. 191
7.4.4 Value of Saved Program Counter ..................................................................... 192
7.4.5 Usage Examples................................................................................................ 193
7.5 Usage Notes ...................................................................................................................... 196
Section 8 Data Transfer Controller (DTC) ..........................................................197
8.1 Features............................................................................................................................. 197
8.2 Register Descriptions........................................................................................................ 199
8.2.1 DTC Mode Register A (MRA) ......................................................................... 200
8.2.2 DTC Mode Register B (MRB).......................................................................... 201
8.2.3 DTC Source Address Register (SAR)............................................................... 203
8.2.4 DTC Destination Address Register (DAR)....................................................... 203
8.2.5 DTC Transfer Count Register A (CRA) ........................................................... 204
8.2.6 DTC Transfer Count Register B (CRB)............................................................ 205
8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE) ................................... 206
8.2.8 DTC Control Register (DTCCR) ...................................................................... 207
8.2.9 DTC Vector Base Register (DTCVBR)............................................................ 209
8.2.10 Bus Function Extending Register (BSCEHR) .................................................. 209
8.3 Activation Sources............................................................................................................ 210
8.4 Location of Transfer Information and DTC Vector Table ................................................ 211
8.5 Operation .......................................................................................................................... 216
8.5.1 Transfer Information Read Skip Function ........................................................ 221
8.5.2 Transfer Information Write-Back Skip Function .............................................. 222
8.5.3 Normal Transfer Mode ..................................................................................... 222
8.5.4 Repeat Transfer Mode....................................................................................... 223
8.5.5 Block Transfer Mode ........................................................................................ 225
8.5.6 Chain Transfer .................................................................................................. 226
8.5.7 Operation Timing.............................................................................................. 228
8.5.8 Number of DTC Execution Cycles ................................................................... 231
8.5.9 DTC Bus Release Timing ................................................................................. 233
8.5.10 DTC Activation Priority Order ......................................................................... 236
8.6 DTC Activation by Interrupt............................................................................................. 237
8.7 Examples of Use of the DTC ............................................................................................ 238
8.7.1 Normal Transfer Mode ..................................................................................... 238
8.7.2 Chain Transfer when Transfer Counter = 0 ...................................................... 239
8.8 Interrupt Sources............................................................................................................... 241
Rev. 1.00 Jun. 26, 2008 Page xiii of xxx