SH7280 Datasheet, PDF (150/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 6 Interrupt Controller (INTC)
UBC
H-UDI
DMAC
CMT
BSC
WDT
MTU2
MTU2S
POE2
ADC
IIC3
SCI
SCIF
USB
RCAN
SSU
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
DTC
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Interrupt
request
SR
I3 I2 I1 I0
CPU
DTCERA to
DTCERE
DMAC
ICR0
ICR2
IBCR
ICR1
IRQRR
IBNR
IPR
IPR01, IPR02,
IPR05 to IPR18
CHCR[11:8]
Module bus
Bus
interface
[Legend]
UBC: User break controller
H-UDI: User debugging interface
DMAC: Direct memory access controller
CMT: Compare match timer
BSC: Bus state controller
WDT: Watchdog timer
MTU2: Multi-function timer pulse unit 2
MTU2S: Multi-function timer pulse unit 2S
POE2: Port output enable 2
ADC:
IIC3:
A/D converter
I²C bus interface 3*¹
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
SSU: Synchronous serial communication unit*¹
USB: USB function module*¹
DTC: Data transfer controller
RCAN: Controller area network*²
INTC
ICR0:
Interrupt control register 0
ICR1:
Interrupt control register 1
ICR2:
Interrupt control register 2
IRQRR:
IRQ interrupt request register
IBCR:
Bank control register
IBNR:
Bank number register
IPR01, IPR02, IPR05 to IPR18: Interrupt priority registers 01, 02, 05 to 18
Notes: 1. Only in SH7286 and SH7285
2. Only in SH7286
Figure 6.1 Block Diagram of INTC
Rev. 1.00 Jun. 26, 2008 Page 120 of 1692
REJ09B0393-0100