SH7280 Datasheet, PDF (309/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Bit
12, 11
10 to 7
6
5 to 2
Bit Name
SW[1:0]
Initial
Value
00
WR[3:0] 1010
WN
0

All 0
R/W Description
R/W Number of Delay Cycles from Address, CS6 Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address, CS6
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
R/W Number of Access Wait Cycles
Specify the number of cycles that are necessary for
read/write access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
R/W External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification of this bit is valid even when the
number of access wait cycles is 0.
0: The external wait input is valid
1: The external wait input is ignored
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Jun. 26, 2008 Page 279 of 1692
REJ09B0393-0100