SH7280 Datasheet, PDF (1377/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.4 Interrupt Sources
This module has two interrupt signals. Table 25.3 shows the interrupt sources and their
corresponding interrupt request signals.
Table 25.3 Interrupt Sources
Interrupt
Register Bit Transfer Type Source
Description
Interrupt
Request
Signal
DMAC/DTC
Activation by
USB Request
USBIFR0 7
(Status)
BRST
Bus reset
USI0 or USI1 ×
6
Bulk-OUT
EP1FULL EP1FIFO full
(EP1)
USI0 or USI1 DREQ0*¹
5
Bulk-IN
4
(EP2)
EP2TR
EP2 transfer request
EP2EMPTY EP2 FIFO empty
USI0 or USI1 ×
USI0 or USI1 DREQ1*²
3
Setup
(EP0s)
SETUPTS
Set command receive
completion
USI0 or USI1 ×
2
Control-OUT EP0oTS
(EP0o)
EP0o receive completion USI0 or USI1 ×
1
Control-IN
EP0iTR
0
(EP0i)
EP0iTS
EP0i transfer request USI0 or USI1 ×
EP0i transmit completion USI0 or USI1 ×
USBIFR1 7

Reserved 


6

Reserved 


5

Reserved 


4

Reserved 


3
(Status)
VBUSMN VBUS monitor
USI0 or USI1 ×
2
Interrupt
1
(EP3)
EP3TR
EP3TS
EP3 transfer request
USI0 or USI1 ×
EP3 transmit completion USI0 or USI1 ×
0
(Status)
VBUSF
USB disconnection
detect
USI0 or USI1 ×
Notes: 1. For bulk-OUT transfer, set the EP1DMAE bit in USBDMAR to enable DMA/DTC
transfer requests.
2. For bulk-IN transfer, set the EP2DMAE bit in USBDMAR to enable DMA/DTC transfer
requests.
Rev. 1.00 Jun. 26, 2008 Page 1347 of 1692
REJ09B0393-0100