SH7280 Datasheet, PDF (260/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 8 Data Transfer Controller (DTC)
Clock (Bφ)
DTC activation
request
DTC request
Internal address
R
W
Vector read
Transfer information
read
Data
transfer
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.14 Example of DTC Operation Timing: Normal Transfer, Repeat Transfer,
DTPR=1 (Activated by On-Chip Peripheral Module; Iφ: Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer
Information is Written in 3 Cycles)
Clock (Bφ)
DTC activation
request
by pins IRQ
DTC request
Internal address
R
W
Vector read
Transfer information
read
Data
transfer
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.15 Example of DTC Operation Timing: Normal Transfer, Repeat Transfer,
(Activated by IRQ; Iφ: Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer
Information is Written in 3 Cycles)
Rev. 1.00 Jun. 26, 2008 Page 230 of 1692
REJ09B0393-0100