SH7280 Datasheet, PDF (508/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
2
TGFC
0
R/(W)*¹ Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0, 3, and 4.
Only 0 can be written, for flag clearing. In channels 1
and 2, bit 2 is reserved. It is always read as 0 and the
write value should always be 0.
[Clearing condition]
• When DTC is activated by TGIC interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to TGFC after reading
TGFC = 1*²
[Setting conditions]
• When TCNT = TGRC and TGRC is functioning as
output compare register
1
TGFB
0
• When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
R/(W)*¹ Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match. Only 0 can be written, for
flag clearing.
[Clearing condition]
• When DTC is activated by TGIB interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to TGFB after reading
TGFB = 1*²
[Setting conditions]
• When TCNT = TGRB and TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal and TGRB is functioning as input
capture register
Rev. 1.00 Jun. 26, 2008 Page 478 of 1692
REJ09B0393-0100