SH7280 Datasheet, PDF (12/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

6.4.5 On-Chip Peripheral Module Interrupts ............................................................. 135
6.5 Interrupt Exception Handling Vector Table and Priority.................................................. 136
6.6 Operation .......................................................................................................................... 145
6.6.1 Interrupt Operation Sequence ........................................................................... 145
6.6.2 Stack after Interrupt Exception Handling ......................................................... 148
6.7 Interrupt Response Time................................................................................................... 149
6.8 Register Banks .................................................................................................................. 155
6.8.1 Banked Register and Input/Output of Banks .................................................... 156
6.8.2 Bank Save and Restore Operations................................................................... 156
6.8.3 Save and Restore Operations after Saving to All Banks................................... 158
6.8.4 Register Bank Exception .................................................................................. 159
6.8.5 Register Bank Error Exception Handling ......................................................... 159
6.9 Data Transfer with Interrupt Request Signals................................................................... 160
6.9.1 Handling Interrupt Request Signals as DTC Activating Sources
and CPU Interrupt Sources but Not as DMAC Activating Sources .................. 162
6.9.2 Handling Interrupt Request Signals as DMAC Activating Sources
but Not as CPU Interrupt Sources..................................................................... 162
6.9.3 Handling Interrupt Request Signals as DTC Activating Sources
but Not as CPU Interrupt Sources or DMAC Activating Sources .................... 162
6.9.4 Handling Interrupt Request Signals as CPU Interrupt Sources
but Not as DTC Activating Sources or DMAC Activating Sources ................. 163
6.10 Usage Note ....................................................................................................................... 164
6.10.1 Timing to Clear an Interrupt Source ................................................................. 164
Section 7 User Break Controller (UBC).............................................................. 165
7.1 Features............................................................................................................................. 165
7.2 Input/Output Pin ............................................................................................................... 167
7.3 Register Descriptions........................................................................................................ 168
7.3.1 Break Address Register_0 (BAR_0)................................................................. 169
7.3.2 Break Address Mask Register_0 (BAMR_0) ................................................... 170
7.3.3 Break Bus Cycle Register_0 (BBR_0).............................................................. 171
7.3.4 Break Address Register_1 (BAR_1)................................................................. 173
7.3.5 Break Address Mask Register_1 (BAMR_1) ................................................... 174
7.3.6 Break Bus Cycle Register_1 (BBR_1).............................................................. 175
7.3.7 Break Address Register_2 (BAR_2)................................................................. 177
7.3.8 Break Address Mask Register_2 (BAMR_2) ................................................... 178
7.3.9 Break Bus Cycle Register_2 (BBR_2).............................................................. 179
7.3.10 Break Address Register_3 (BAR_3)................................................................. 181
7.3.11 Break Address Mask Register_3 (BAMR_3) ................................................... 182
7.3.12 Break Bus Cycle Register_3 (BBR_3).............................................................. 183
Rev. 1.00 Jun. 26, 2008 Page xii of xxx