SH7280 Datasheet, PDF (917/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
18.3.2 SS Control Register L (SSCRL)
SSCRL selects operating mode, software reset, and transmit/receive data length.
Bit: 7
6
5
4
3
2
1
0
- SSUMS SRES -
-
-
DATS[1:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R/W R/W R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W
7
—
0
R
6
SSUMS 0
R/W
5
SRES
0
R/W
4 to 2 
All 0
R
Description
Reserved
The bit is always read as 0. The write value should
always be 0.
Selects transfer mode from SSU mode and clock
synchronous mode.
0: SSU mode
1: Clock synchronous mode
Software Reset
Setting this bit to 1 forcibly resets the SSU internal
sequencer. After that, this bit is automatically cleared.
The ORER, TEND, TDRE, RDRF, and CE bits in SSSR
and the TE and RE bits in SSER are also initialized.
Values of other bits for SSU registers are held.
To stop transfer, set this bit to 1 to reset the SSU
internal sequencer.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Jun. 26, 2008 Page 887 of 1692
REJ09B0393-0100