SH7280 Datasheet, PDF (905/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 17 Serial Communication Interface with FIFO (SCIF)
17.5 SCIF Interrupts
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive FIFO data full (RXI), and break (BRI).
Table 17.12 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register
(SCFSR) is set to 1, a TXI interrupt request is generated. The DMAC or DTC can be activated and
data transfer performed by this TXI interrupt request. At DMAC activation, an interrupt request is
not sent to the CPU.
When an RXI request is enabled by the RIE bit and the RDFE flag or the DR flag in SCFSR is set
to 1, an RXI interrupt request is generated. The DMAC or DTC can be activated and data transfer
performed by this RXI interrupt request. At DMAC activation, an interrupt request is not sent to
the CPU. The RXI interrupt request caused by the DR flag is generated only in asynchronous
mode.
When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests only an ERI interrupt
without requesting an RXI interrupt.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR.
Table 17.12 SCIF Interrupt Sources
Interrupt
Source
BRI
ERI
RXI
TXI
Description
DMAC or DTC Priority on
Activation
Reset Release
Interrupt initiated by break (BRK) or overrun error Not possible High
(ORER)
Interrupt initiated by receive error (ER)
Not possible
Interrupt initiated by receive FIFO data full (RDF) or Possible
data ready (DR)
Interrupt initiated by transmit FIFO data empty
Possible
(TDFE)
Low
Rev. 1.00 Jun. 26, 2008 Page 875 of 1692
REJ09B0393-0100