SH7280 Datasheet, PDF (318/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Bit
12
11, 10
9
8, 7
6, 5
Bit Name
Initial
Value R/W Description

0
R Reserved
This bit is always read as 0. The write value should
always be 0.
WTRCD[1:0] 01
R/W Number of Wait Cycles between ACTV Command and
READ(A)/WRIT(A) Command
Specify the minimum number of wait cycles from
issuing the ACTV command to issuing the
READ(A)/WRIT(A) command. The setting for areas 2
and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles

0
R Reserved
This bit is always read as 0. The write value should
always be 0.
A3CL[1:0] 10
R/W CAS Latency for Area 3
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles

All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Jun. 26, 2008 Page 288 of 1692
REJ09B0393-0100