SH7280 Datasheet, PDF (723/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 13 Port Output Enable 2 (POE2)
13.3 Register Descriptions
The POE2 has the following registers.
All these registers are initialized by a power-on reset, but are not initialized by a manual reset or in
sleep mode, software standby mode, or module standby mode.
Table 13.3 Register Configuration
Register Name
Input level control/status register 1
Output level control/status register 1
Input level control/status register 2
Output level control/status register 2
Input level control/status register 3
Software port output enable register
Port output enable control register 1
Port output enable control register 2
Abbreviation R/W
ICSR1
R/W
OCSR1
R/W
ICSR2
R/W
OCSR2
R/W
ICSR3
R/W
SPOER
R/W
POECR1
R/W
POECR2
R/W
Initial
Value
H'0000
H'0000
H'0000
H'0000
H'0000
H'00
H'00
H'7700
Address
H'FFFE5000
H'FFFE5002
H'FFFE5004
H'FFFE5006
H'FFFE5008
H'FFFE500A
H'FFFE500B
H'FFFE500C
Access
Size
16
16
16
16
16
8
8
16
Rev. 1.00 Jun. 26, 2008 Page 693 of 1692
REJ09B0393-0100