SH7280 Datasheet, PDF (138/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 5 Exception Handling
5.5 Interrupts
5.5.1 Interrupt Sources
Table 5.7 shows the sources that start up interrupt exception handling. These are divided into
NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules.
Table 5.7 Interrupt Sources
Type
NMI
User break
H-UDI
IRQ
On-chip peripheral module
Request Source
NMI pin (external input)
User break controller (UBC)
User debugging interface (H-UDI)
IRQ0 to IRQ7 pins (external input)
A/D converter (ADC)
Controller area network (RCAN-ET)
Direct memory access controller (DMAC)
Compare match timer (CMT)
Bus state controller (BSC)
Watchdog timer (WDT)
USB function module (USB)
Multi-function timer pulse unit 2 (MTU2)
Multi-function timer pulse unit 2S (MTU2S)
Port output enable 2 (POE2)
I²C bus interface 3 (IIC3)
Synchronous serial communication unit (SSU)
Serial communication interface (SCI)
Serial communication interface with FIFO (SCIF)
Number of
Sources
1
1
1
8
3
4
16
2
1
1
4
28
13
3
5
3
16
4
Each interrupt source is allocated a different vector number and vector table offset. See table 6.4
in section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table
address offsets.
Rev. 1.00 Jun. 26, 2008 Page 108 of 1692
REJ09B0393-0100