SH7280 Datasheet, PDF (1476/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
(b) SCO Download Request and Interrupt Request
Download of the on-chip programming/erasing program that is initiated by setting the SCO bit in
FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover.
Operation when the SCO download request and interrupt request conflicts is described below.
1. Contention between SCO download request and interrupt request
Figure 26.18shows the timing of contention between execution of the instruction that sets the
SCO bit in FCCS to 1 and interrupt acceptance.
CPU cycle
CPU operation for instruction
that sets SCO bit to 1
Interrupt acceptance
n
Fetch
n+1
Decoding
(a)
n+2
Execution
(b)
n+3
Execution
n+4
Execution
(a) When the interrupt is accepted at the (n + 1) cycle or before
After the interrupt processing completes, the SCO bit is set to 1 and download is executed.
(b) When the interrupt is accepted at the (n + 2) cycle or later
The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated.
Figure 26.20 Timing of Contention between SCO Download Request and Interrupt Request
2. Generation of interrupt requests during downloading
Ensure that interrupts are not generated during downloading that is initiated by the SCO bit.
Rev. 1.00 Jun. 26, 2008 Page 1446 of 1692
REJ09B0393-0100