SH7280 Datasheet, PDF (76/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 2 CPU
Operation
Classification Types Code
Function
No. of
Instructions
System
14
CLRT
T bit clear
36
control
CLRMAC MAC register clear
LDBANK Register restoration from specified register
bank entry
LDC
Load to control register
LDS
Load to system register
NOP
No operation
RESBANK Register restoration from register bank
RTE
Return from exception handling
SETT
T bit set
SLEEP Transition to power-down mode
STBANK Register save to specified register bank entry
STC
Store control register data
STS
Store system register data
TRAPA Trap exception handling
Bit
10
BAND
Bit AND
14
manipulation
BCLR
Bit clear
BLD
Bit load
BOR
Bit OR
BSET
Bit set
BST
Bit store
BXOR
Bit exclusive OR
BANDNOT Bit NOT AND
BORNOT Bit NOT OR
BLDNOT Bit NOT load
Total:
91
197
Rev. 1.00 Jun. 26, 2008 Page 46 of 1692
REJ09B0393-0100