SH7280 Datasheet, PDF (114/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 4 Clock Pulse Generator (CPG)
4.4.2 MTU2S Clock Frequency Control Register (MCLKCR)
MCLKCR is an 8-bit readable/writable register. MCLKCR can be accessed only in byte units.
MCLKCR is initialized to H'43 only by a power-on reset. MCLKCR retains its previous value by
a manual reset or in software standby mode.
Bit: 7
6
5
4
3
2
1
0
MSSCS[1:0]
-
-
-
-
MSDIVS[1:0]
Initial value: 0
1
0
0
0
0
1
1
R/W: R/W R/W R
R
R
R R/W R/W
Bit
7, 6
5 to 2
1, 0
Bit Name
Initial
Value
MSSCS[1:0] 01

All 0
MSDIVS[1:0] 11
R/W
R/W
R
R/W
Description
Source Clock Select
These bits select the source clock.
00: Clock stop
01: PLL output clock
10: Reserved (setting prohibited)
11: Reserved (setting prohibited)
Reserved
These bits are always read as 0. The write value
should always be 0.
Division Ratio Select
These bits specify the frequency division ratio of the
source clock. Set these bits so that the output clock is
100 MHz or less, and also an integer multiple of the
peripheral clock frequency (Pφ).
00: × 1
01: × 1/2
10: Setting prohibited
11: × 1/4
Rev. 1.00 Jun. 26, 2008 Page 84 of 1692
REJ09B0393-0100