SH7280 Datasheet, PDF (771/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 15 Watchdog Timer (WDT)
Initial
Bit
Bit Name Value R/W Description
2 to 0 CKS[2:0] 000
R/W Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is
shown in the table is the value when the peripheral
clock (Pφ) is 40 MHz.
Bits 2 to 0
Clock Ratio Overflow Cycle
000:
1 × Pφ
6.4 µs
001:
1/64 × Pφ
409.6 µs
010:
1/128 × Pφ
819.2 ms
011:
1/256 × Pφ
1.64 ms
100:
1/512 × Pφ
3.3 ms
101:
1/1024 × Pφ 6.6 ms
110:
1/4096 × Pφ 26.2 ms
111:
1/16384 × Pφ 104.9 ms
Note: If bits CKS[2:0] are modified when the WDT is
running, the up-count may not be performed
correctly. Ensure that these bits are modified
only when the WDT is not running.
Rev. 1.00 Jun. 26, 2008 Page 741 of 1692
REJ09B0393-0100