SH7280 Datasheet, PDF (217/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
10
SCMFD1 0
R/W I Bus Cycle Condition Match Flag 1
When the I bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 1 does not
match
1: The I bus cycle condition for channel 1 matches
9
SCMFD2 0
R/W I Bus Cycle Condition Match Flag 2
When the I bus cycle condition in the break conditions
set for channel 2 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 2 does not
match
1: The I bus cycle condition for channel 2 matches
8
SCMFD3 0
R/W I Bus Cycle Condition Match Flag 3
When the I bus cycle condition in the break conditions
set for channel 3 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 3 does not
match
1: The I bus cycle condition for channel 3 matches
7
PCB3
0
R/W PC Break Select 3
Selects the break timing of the instruction fetch cycle
for channel 3 as before or after instruction execution.
0: PC break of channel 3 is generated before
instruction execution
1: PC break of channel 3 is generated after instruction
execution
6
PCB2
0
R/W PC Break Select 2
Selects the break timing of the instruction fetch cycle
for channel 2 as before or after instruction execution.
0: PC break of channel 2 is generated before
instruction execution
1: PC break of channel 2 is generated after instruction
execution
Rev. 1.00 Jun. 26, 2008 Page 187 of 1692
REJ09B0393-0100