SH7280 Datasheet, PDF (756/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 14 Compare Match Timer (CMT)
14.2.2 Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates compare match generation, enables or disables
interrupts, and selects the counter input clock.
CMCSR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its
previous value in module standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
CMF CMIE
-
-
-
-
CKS[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/(W)* R/W R
R
R
R R/W R/W
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
15 to 8
Bit Name

7
CMF
6
CMIE
Initial
Value
All 0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)* Compare Match Flag
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match.
[Clearing condition]
• When 0 is written to CMF after reading CMF = 1
• When data is transferred after the DTC has been
activated by CMI (except when the DTC transfer
counter value has become H'000).
• When data is transferred after the DMAC has been
activated by CMI
1: CMCNT and CMCOR values match
R/W Compare Match Interrupt Enable
Enables or disables compare match interrupt (CMI)
generation when CMCNT and CMCOR values match
(CMF = 1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
Rev. 1.00 Jun. 26, 2008 Page 726 of 1692
REJ09B0393-0100