SH7280 Datasheet, PDF (871/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 17 Serial Communication Interface with FIFO (SCIF)
Table 17.3 SCSMR Settings
n
Clock Source
0
Pφ
1
Pφ/4
2
Pφ/16
3
Pφ/64
CKS1
0
0
1
1
SCSMR Settings
CKS0
0
1
0
1
The bit rate error in asynchronous is given by the following formula:
• When the ABCS bit in serial extended mode register (SCSEMR) is 0
Error (%) =
Pφ × 10⁶
- 1 × 100
(N + 1) × B × 64 × 2^2n-1
• When the ABCS bit in serial extended mode register (SCSEMR) is 1
Error (%) =
Pφ × 10⁶
- 1 × 100
(N + 1) × B × 32 × 2^2n-1
Table 17.4 lists examples of SCBRR settings in asynchronous mode, and table 17.5 lists examples
of SCBRR settings in clocked synchronous mode.
Rev. 1.00 Jun. 26, 2008 Page 841 of 1692
REJ09B0393-0100