SH7280 Datasheet, PDF (126/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 5 Exception Handling
Type
Exception Handling
Priority
Interrupt
On-chip peripheral modules Port output enable 2 (POE2): OEI1 and
OEI2 interrupts
High
Multi-function timer pulse unit 2S (MTU2S)
Port output enable 2 (POE2): OEI3
interrupt
USB function module (USB) USI0/USI1
I²C bus interface 3 (IIC3)
Synchronous serial communication unit
(SSU)
Serial communication interface (SCI)
Serial communication interface with FIFO
(SCIF)
Instruction Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Slot illegal instructions (undefined code placed directly after a delayed
branch instruction*¹, instructions that rewrite the PC*², 32-bit
instructions*³, RESBANK instruction, DIVS instruction, and DIVU
instruction)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.
3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.
Rev. 1.00 Jun. 26, 2008 Page 96 of 1692
REJ09B0393-0100