SH7280 Datasheet, PDF (1432/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
Table 26.6 Usable Parameters and Target Modes
Name of
Parameter
Pro-
Abbrevia- Down- Initiali- gram-
Initial
tion
load zation ming Erasure R/W Value
Allocation
Download pass/fail DPFR √
—
——
result
R/W Undefined On-chip
RAM*
Flash pass/fail
result
FPFR
—
√
√
√
R/W Undefined R0 of CPU
Flash
FPEFEQ —
√
programming/
erasing frequency
control
——
R/W Undefined R4 of CPU
Flash user branch FUBRA —
√
address set
——
R/W Undefined R5 of CPU
Flash multipurpose FMPAR —
—
√
—
address area
R/W Undefined R5 of CPU
Flash multipurpose FMPDR —
—
√
—
data destination
area
R/W Undefined R4 of CPU
Flash erase block FEBS
—
—
select
—√
R/W Undefined R4 of CPU
Note: * One byte of start address of download destination specified by FTDAR
Rev. 1.00 Jun. 26, 2008 Page 1402 of 1692
REJ09B0393-0100