SH7280 Datasheet, PDF (1357/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.1 USB Interrupt Flag Register 0 (USBIFR0)
Together with USB interrupt flag register 1 (USBIFR1), USBIFR0 indicates interrupt status
information required by the application. When an interrupt occurs, the corresponding bit is set to 1
and an interrupt request is sent to the CPU according to the combination with USB interrupt
enable register 0 (USBIER0). Clearing is performed by writing 0 to the bit to be cleared, and 1 to
the other bits. However, EP1 FULL and EP2 EMPTY are status bits, and cannot be cleared.
USBIFR0 is initialized to H'10 by a power-on reset.
Bit:
Initial value:
R/W:
7
BRST
0
R/W
6
EP1
FULL
0
R
5
4
3
2
1
0
EP2TR
EP2
EMPTY
SETUP
TS
EP0oTS
EP0iTR
EP0iTS
0
1
0
0
0
0
R/W R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
BRST
0
R/W Bus Reset
Set to 1 when the bus reset signal is detected on the
USB bus.
6
EP1FULL 0
R
EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data normally from the host, and holds a value of 1 as
long as there is valid data in the FIFO buffer. EP1
FULL is a status bit, and cannot be cleared.
5
EP2TR
0
R/W EP2 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 2 is
received from the host. A NACK handshake is
returned to the host until data is written to the FIFO
buffer and packet transmission is enabled.
4
EP2EMPTY 1
R
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written. EP2 EMPTY is a status bit, and cannot be
cleared.
Rev. 1.00 Jun. 26, 2008 Page 1327 of 1692
REJ09B0393-0100