SH7280 Datasheet, PDF (289/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 7)
CSnBCR is a 32-bit readable/writable register that specifies the type of memory connected to a
space, data bus width of an area, endian, and the number of waits between access cycles. This
register is initialized to H'36DB0x00 by a power-on reset and retains the value by a manual reset
and in software standby mode.
Do not access external memory other than area 0 until CSnBCR initial setting is completed.
Idle cycles may be inserted even when they are not specified. For details, see section 9.5.10, Wait
between Access Cycles.
Bit: 31
-
Initial value: 0
R/W: R
30 29 28
IWW[2:0]
0
1
1
R/W R/W R/W
27 26 25
IWRWD[2:0]
0
1
1
R/W R/W R/W
24 23 22
IWRWS[2:0]
0
1
1
R/W R/W R/W
21 20 19
IWRRD[2:0]
0
1
1
R/W R/W R/W
18 17 16
IWRRS[2:0]
0
1
1
R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
TYPE[2:0]
ENDIAN BSZ[1:0]
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0* 1* 0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
R
Bit
Bit Name
31

30 to 28 IWW[2:0]
Initial
Value
0
011
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Idle Cycles between Write-Read Cycles and Write-
Write Cycles
These bits specify the number of idle cycles to be
inserted after the access to a memory that is
connected to the space. The target access cycles are
the write-read cycle and write-write cycle.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Rev. 1.00 Jun. 26, 2008 Page 259 of 1692
REJ09B0393-0100