SH7280 Datasheet, PDF (923/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
Initial
Bit
Bit Name Value R/W
Description
1
RDRF
0
0
CE
0
R/W
Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
• When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
[Clearing conditions]
• When writing 0 after reading RDRF = 1
• When reading receive data from SSRDR
• When transmit data is read into SSRDR while the
DISEL bit in MRB of the DTC is 0 if the DMAC/DTC
is activated by an SSRXI interrupt and then DTC is
activated
R/W
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave device), an incomplete error
occurs because it is determined that a master device
has terminated the transfer. In addition, an incomplete
error occurs when the next serial reception starts as
RDRF=1 in the state of SSUMS=0 (SSU mode) or
MSS=0 (slave device), then the SCS pin is changed to
1 after the RDRF is cleared to 0 while the SSRDR was
read before data reception is completed. Data reception
does not continue while the CE bit is set to 1. Serial
transmission also does not continue. Reset the SSU
internal sequencer by setting the SRES bit in SSCRL to
1 before resuming transfer after incomplete error.
[Setting conditions]
• When a low level is input to the SCS pin in master
mode (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in
slave mode (the MSS bit in SSCRH is cleared to 0)
• When the SCS pin is changed to 1, the next
reception starts as RDRF=1, then after having read
the SSRDR before data reception is completed
during transfer in slave mode (the MSS bit in
SSCRH is cleared to 0)
[Clearing condition]
• When writing 0 after reading CE = 1
Rev. 1.00 Jun. 26, 2008 Page 893 of 1692
REJ09B0393-0100