SH7280 Datasheet, PDF (1548/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 29 User Debugging Interface (H-UDI)
29.4.2 Reset Configuration
Table 29.4 Reset Configuration
ASEMD0*¹
RES
TRST
Chip State
H
L
L
Power-on reset and H-UDI reset
H
Power-on reset
H
L
H-UDI reset only
H
Normal operation
L
L
L
Reset hold*²
H
Power-on reset
H
L
H-UDI reset only
H
Normal operation
Notes: 1. Performs normal mode and ASE mode settings
ASEMD0 = H, normal mode
ASEMD0 = L, ASE mode
2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RES pin is
negated. In this state, the CPU does not start up. When TRST is driven high, H-UDI
operation is enabled, but the CPU does not start up. The reset hold state is cancelled
by a power-on reset.
29.4.3 TDO Output Timing
The initial value of the TDO change timing is to perform data output from the TDO pin on the
TCK falling edge. However, setting a TDO change timing switch command in SDIR via the H-
UDI pin and passing the Update-IR state synchronizes the TDO change timing to the TCK rising
edge. Thereafter the TDO change timing cannot be changed unless a power-on reset that asserts
the TRST pin simultaneously is performed.
TCK
TDO
(after execution of TDO change
timing switch command)
TDO
(initial value)
t_TDOD
t_TDOD
Figure 29.3 H-UDI Data Transfer Timing
Rev. 1.00 Jun. 26, 2008 Page 1518 of 1692
REJ09B0393-0100