SH7280 Datasheet, PDF (17/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

11.5 Interrupt Sources............................................................................................................... 615
11.5.1 Interrupt Sources and Priorities......................................................................... 615
11.5.2 DMAC and DTC Activation ............................................................................. 617
11.5.3 A/D Converter Activation................................................................................. 618
11.6 Operation Timing.............................................................................................................. 620
11.6.1 Input/Output Timing ......................................................................................... 620
11.6.2 Interrupt Signal Timing..................................................................................... 627
11.7 Usage Notes ...................................................................................................................... 633
11.7.1 Module Standby Mode Setting ......................................................................... 633
11.7.2 Input Clock Restrictions ................................................................................... 633
11.7.3 Caution on Period Setting ................................................................................. 634
11.7.4 Contention between TCNT Write and Clear Operations.................................. 634
11.7.5 Contention between TCNT Write and Increment Operations........................... 635
11.7.6 Contention between TGR Write and Compare Match ...................................... 636
11.7.7 Contention between Buffer Register Write and Compare Match ..................... 637
11.7.8 Contention between Buffer Register Write and TCNT Clear ........................... 638
11.7.9 Contention between TGR Read and Input Capture........................................... 639
11.7.10 Contention between TGR Write and Input Capture.......................................... 640
11.7.11 Contention between Buffer Register Write and Input Capture ......................... 641
11.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection .. 641
11.7.13 Counter Value during Complementary PWM Mode Stop ................................ 643
11.7.14 Buffer Operation Setting in Complementary PWM Mode ............................... 643
11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 644
11.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 645
11.7.17 Contention between Overflow/Underflow and Counter Clearing..................... 646
11.7.18 Contention between TCNT Write and Overflow/Underflow............................ 647
11.7.19 Cautions on Transition from Normal Operation
or PWM Mode 1 to Reset-Synchronized PWM Mode...................................... 647
11.7.20 Output Level in Complementary PWM Mode
and Reset-Synchronized PWM Mode ............................................................... 648
11.7.21 Interrupts in Module Standby Mode ................................................................. 648
11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection........ 648
11.8 MTU2 Output Pin Initialization........................................................................................ 649
11.8.1 Operating Modes............................................................................................... 649
11.8.2 Reset Start Operation ........................................................................................ 649
11.8.3 Operation in Case of Re-Setting Due to Error during Operation, etc. .............. 650
11.8.4 Overview of Initialization Procedures and Mode Transitions
in Case of Error during Operation, etc. ............................................................. 651
Rev. 1.00 Jun. 26, 2008 Page xvii of xxx