SH7280 Datasheet, PDF (266/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 8 Data Transfer Controller (DTC)
8.5.10 DTC Activation Priority Order
If multiple DTC activation requests are generated while the DTC is inactive, whether to start the
DTC transfer from the first activation request or according to the DTC activation priority can be
selected through the DTPR bit setting in the bus function extending register (BSCEHR). If
multiple activation requests are generated while the DTC is active, transfer is performed according
to the DTC activation priority. Figure 8.17 shows an example of DTC activation according to the
priority.
(1) DTPR = 0
DTC is inactive
Transfer is started for the first activation request
DTC is active
Transfer is performed according to the priority
Internal bus
Other than DTC
DTC
(request 3)
DTC
(request 1)
DTC
(request 2)
DTC activation request 1
(High priority)
DTC activation request 2
(Medium priority)
DTC activation request 3
(Low priority)
Priority
determination
(2) DTPR = 1
DTC is inactive
Transfer is started according to the priority
DTC is active
Transfer is performed according to the priority
Internal bus
Other than DTC
DTC
(request 1)
DTC
(request 2)
DTC
(request 3)
DTC activation request 1
(High priority)
DTC activation request 2
(Medium priority)
DTC activation request 3
(Low priority)
Priority
determination
Priority
determination
Figure 8.17 Example of DTC Activation According to Priority
Rev. 1.00 Jun. 26, 2008 Page 236 of 1692
REJ09B0393-0100