SH7280 Datasheet, PDF (722/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 13 Port Output Enable 2 (POE2)
Table 13.2 shows output-level comparisons with pin combinations.
Table 13.2 Pin Combinations
Pin Combination
PE9/TIOC3B and PE11/TIOC3D
PE12/TIOC4A and PE13/TIOC4C
PE14/TIOC4B and PE15/TIOC4D
PE5/PD10/PD29/TIOC3BS and
PE6/PD11/PD28/TIOC3DS
PE0/PD12/PD27/TIOC4AS and
PE2/PD14/PD25/TIOC4CS
PE1/PD13/PD26/TIOC4BS and
PE3/PD15/PD24/TIOC4DS
I/O
Description
Output
The high-current pins for the MTU2 are placed in
high-impedance state when the pins
simultaneously output an active level for one or
more cycles of the peripheral clock (Pφ). (In the
case of TOCS = 0 in timer output control register 1
(TOCR1) in the MTU2, low level when the output
level select P (OLSP) bit is 0, or high level when
the OLSP bit is 1. In the case of TOCS = 1, low
level when the OLS3N, OLS3P, OLS2N, OLS2P,
OLS1N, and OLS1P bits are 0 in TOCR2, or high
level when these bits are 1.)
This active level comparison is done when the
MTU2 output function or general output function is
selected in the pin function controller. If another
function is selected, the output level is not
checked.
Pin combinations for output comparison and high-
impedance control can be selected by POE2
registers.
Output
The high-current pins for the MTU2S are placed in
high-impedance state when the pins
simultaneously output an active level for one or
more cycles of the peripheral clock (Pφ). (In the
case of TOCS = 0 in timer output control register
1S (TOCR1S) in the MTU2S, low level when the
output level select P (OLSP) bit is 0, or high level
when the OLSP bit is 1. In the case of TOCS = 1,
low level when the OLS3N, OLS3P, OLS2N,
OLS2P, OLS1N, and OLS1P bits are 0 in
TOCR2S, or high level when these bits are 1.)
This active level comparison is done when the
MTU2S output function or general output function
is selected in the pin function controller. If another
function is selected, the output level is not
checked.
Pin combinations for output comparison and high-
impedance control can be selected by POE2
registers.
Rev. 1.00 Jun. 26, 2008 Page 692 of 1692
REJ09B0393-0100