SH7280 Datasheet, PDF (19/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

14.5 Usage Notes ...................................................................................................................... 732
14.5.1 Conflict between Write and Compare-Match Processes of CMCNT ............... 732
14.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ............... 733
14.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT................. 734
14.5.4 Compare Match between CMCNT and CMCOR ............................................. 734
Section 15 Watchdog Timer (WDT)....................................................................735
15.1 Features............................................................................................................................. 735
15.2 Input/Output Pin ............................................................................................................... 737
15.3 Register Descriptions........................................................................................................ 738
15.3.1 Watchdog Timer Counter (WTCNT)................................................................ 738
15.3.2 Watchdog Timer Control/Status Register (WTCSR)........................................ 739
15.3.3 Watchdog Reset Control/Status Register (WRCSR) ........................................ 742
15.3.4 Notes on Register Access.................................................................................. 743
15.4 WDT Usage ...................................................................................................................... 745
15.4.1 Changing the Frequency ................................................................................... 745
15.4.2 Using Watchdog Timer Mode........................................................................... 746
15.4.3 Using Interval Timer Mode .............................................................................. 748
15.5 Usage Notes ...................................................................................................................... 749
15.5.1 Timer Variation................................................................................................. 749
15.5.2 Prohibition against Setting H'FF to WTCNT.................................................... 749
15.5.3 System Reset by WDTOVF Signal................................................................... 749
15.5.4 Manual Reset in Watchdog Timer Mode .......................................................... 750
Section 16 Serial Communication Interface (SCI) ..............................................751
16.1 Features............................................................................................................................. 751
16.2 Input/Output Pins.............................................................................................................. 753
16.3 Register Descriptions........................................................................................................ 754
16.3.1 Receive Shift Register (SCRSR)....................................................................... 755
16.3.2 Receive Data Register (SCRDR) ...................................................................... 755
16.3.3 Transmit Shift Register (SCTSR) ..................................................................... 756
16.3.4 Transmit Data Register (SCTDR)..................................................................... 756
16.3.5 Serial Mode Register (SCSMR)........................................................................ 756
16.3.6 Serial Control Register (SCSCR)...................................................................... 760
16.3.7 Serial Status Register (SCSSR) ........................................................................ 763
16.3.8 Serial Port Register (SCSPTR) ......................................................................... 769
16.3.9 Serial Direction Control Register (SCSDCR)................................................... 771
16.3.10 Bit Rate Register (SCBRR) .............................................................................. 772
Rev. 1.00 Jun. 26, 2008 Page xix of xxx