SH7280 Datasheet, PDF (144/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 5 Exception Handling
5.7 When Exception Sources Are Not Accepted
When an address error, register bank error (overflow), or interrupt is generated immediately after a
delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown
in table 5.10. When this happens, it will be accepted when an instruction that can accept the
exception is decoded.
Table 5.10 Exception Source Generation Immediately after Delayed Branch Instruction
Exception Source
Point of Occurrence
Address Error
Register Bank Error
(Overflow)
Interrupt
Immediately after a delayed Not accepted
branch instruction^*
Not accepted
Not accepted
Note: * Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Rev. 1.00 Jun. 26, 2008 Page 114 of 1692
REJ09B0393-0100