SH7280 Datasheet, PDF (1068/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Bit 3 — Reset Status Bit (GSR3): Indicates whether the RCAN-ET is in the reset state or not.
Bit 3 : GSR3
0
1
Description
RCAN-ET is not in the reset state
Reset state (Initial value)
[Setting condition] After an RCAN-ET internal reset (due to SW or HW reset)
Bit 2 — Message Transmission in progress Flag (GSR2): Flag that indicates to the CPU if the
RCAN-ET is in Bus Off or transmitting a message or an error/overload flag due to error detected
during transmission. The timing to set TXACK is different from the time to clear GSR2. TXACK
is set at the 7^th bit of End Of Frame. GSR2 is set at the 3^rd bit of intermission if there are no more
messages ready to be transmitted. It is also set by arbitration lost, bus idle, reception, reset or halt
transition.
Bit 2 : GSR2
0
1
Description
RCAN-ET is in Bus Off or a transmission is in progress
[Setting condition] Not in Bus Off and no transmission in progress (Initial
value)
Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning.
Bit 1 : GSR1
0
1
Description
[Reset condition] When (TEC < 96 and REC < 96) or Bus Off (Initial value)
[Setting condition] When 96 ≤ TEC < 256 or 96 ≤ REC < 256
Note: REC is incremented during Bus Off to count the recurrences of 11 recessive bits as
requested by the Bus Off recovery sequence. However the flag GSR1 is not set in Bus Off.
Bit 0—Bus Off Flag (GSR0): Flag that indicates that RCAN-ET is in the bus off state.
Bit 0 : GSR0
0
1
Description
[Reset condition] Recovery from bus off state or after a HW or SW reset
(Initial value)
[Setting condition] When TEC ≥ 256 (bus off state)
Note: Only the lower 8 bits of TEC are accessible from the user interface. The 9^th bit is
equivalent to GSR0.
Rev. 1.00 Jun. 26, 2008 Page 1038 of 1692
REJ09B0393-0100