SH7280 Datasheet, PDF (1397/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
USB function
DMA function
OUT token reception
Space
in EP1 FIFO?
YES
NO
NACK
Data reception from host
ACK
Set EP1 FIFO full status ^{Interrupt request to CPU*}
(USBIFR0/EP1 FULL = 1)
Application
Set I[3:0] bits in SR
Set bits 15 to 12 in IPR06
(enable interrupts)
Set transfer information
(SAR_0, DAR_0, CHCR_0,
DMAOR, DMARS0)
Disable EP1 FIFO full interrupt
(USBIER0/EP1 FULL = 0)
Read USBEP1 receive data
size register (USBEPSZ1)
Set transfer information
(DMATCR_0)
[1]
Activate DMA
DMA transfer
request
Set EP1DMAE bit in USBDMAR
to 1
Interrupt request
DMA transfer end ^{to CPU} Clear EP1DMAE bit in USBDMAR
Set TE bit in CHCR
to 0 and clear TE bit in CHCR
Data transfer end
interrupt
Enable EP1 FIFO full interrupt
(USBIER0/EP1 FULL = 1)
Both
Interrupt request to CPU*
EP1 FIFOs empty? _NO
YES
Clear EP1 FIFO full status
(USBIFR0/EP1 FULL = 0)
[1] Set DMATCR_0 to the same value as the USBEP1 receive data size register (USBEPSZ1).
Note: * To generate an interrupt request to the CPU, enable the EP1 FULL interrupt (USBIER0/EP1 FULL = 1).
Figure 25.17 Example of DMA Transfer (Channel 0) for Bulk-OUT Transfer (EP1)
(When Receive Data Size Cannot be Determined Before Receiving Out Token)
Rev. 1.00 Jun. 26, 2008 Page 1367 of 1692
REJ09B0393-0100