SH7280 Datasheet, PDF (849/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 17 Serial Communication Interface with FIFO (SCIF)
Section 17 Serial Communication Interface with FIFO
(SCIF)
This LSI has one channel of serial communication interface with FIFO (SCIF) that supports both
asynchronous and clocked synchronous serial communication. It also has 16-stage FIFO registers
for both transmission and reception independently for each channel that enable this LSI to perform
efficient high-speed continuous communication.
17.1 Features
• Asynchronous serial communication:
 Serial data communication is performed by start-stop in character units. The SCIF can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
 Data length: 7 or 8 bits
 Stop bit length: 1 or 2 bits
 Parity: Even, odd, or none
 Receive error detection: Parity, framing, and overrun errors
 Break detection: Break is detected when a framing error is followed by at least one frame
at the space 0 level (low level). It is also detected by reading the RXD level directly from
the serial port register when a framing error occurs.
• Clocked synchronous serial communication:
 Serial data communication is synchronized with a clock signal. The SCIF can communicate
with other chips having a clocked synchronous communication function. There is one serial
data communication format.
 Data length: 8 bits
 Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the
SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so
high-speed continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
Rev. 1.00 Jun. 26, 2008 Page 819 of 1692
REJ09B0393-0100