SH7280 Datasheet, PDF (390/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Table 9.17 Relationship between Bus Width, Access Size, and Number of Bursts
Bus Width Access Size CSnWCR. BST[1:0] Bits Number of Bursts Access Count
8 bits
8 bits
Not affected
1
1
16 bits
Not affected
2
1
32 bits
Not affected
4
1
16 bytes
x0
16
1
10
4
4
16 bits
8 bits
Not affected
1
1
16 bits
Not affected
1
1
32 bits
Not affected
2
1
16 bytes
00
8
1
01
2
4
10*
4
2
2, 4, 2
3
Note: * When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in
CSnWCR are 10, the number of bursts and access count depend on the access start
address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4
or H'xxxC, 2-4-2 burst access is performed.
Rev. 1.00 Jun. 26, 2008 Page 360 of 1692
REJ09B0393-0100