SH7280 Datasheet, PDF (391/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
CK
A25 to A0
T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2
CSn
RD/WR
RD
D15 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.35 Burst ROM Access Timing (Clock Asynchronous)
(Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First
Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)
Rev. 1.00 Jun. 26, 2008 Page 361 of 1692
REJ09B0393-0100