SH7280 Datasheet, PDF (1456/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
(2) Programming Procedure in User Program Mode
The procedures for download, initialization, and programming are shown in figure 26.13.
Start programming
procedure program
Select on-chip program
to be downloaded and
set download destination
by FTDAR
(2.1)
Set FKEY to H'A5
After clearing VBR,
set SCO to 1 and
execute download
(2.2)
(2.3)
Clear FKEY to 0
(2.4)
DPFR = 0?
(2.5)
No
Yes _{Download error processing}
Set the FPEFEQ and
FUBRA parameters
(2.6)
Initialization
JSR FTDAR setting+32
(2.7)
FPFR = 0?
(2.8)
No
Yes _{Initialization error processing}
1
1
Set FKEY to H'5A
(2.9)
Set parameter to R4 and
R5 (FMPAR and FMPDR)
(2.10)
Programming
(2.11)
JSR FTDAR setting+16
FPFR = 0?
(2.12)
No
Yes
Clear FKEY and
programming
error processing
No
Required data
programming is
(2.13)
completed?
Yes
Clear FKEY to 0
(2.14)
End programming
procedure program
Figure 26.13 Programming Procedure
The details of the programming procedure are described below. The procedure program must be
executed in an area other than the flash memory to be programmed. Especially the part where the
SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. Specify
1/4:1/4:1/4 (initial value) as the frequency division ratios of an internal clock (Iφ), a bus clock
(Bφ), and a peripheral clock (Pφ) through the frequency control register (FRQCR).
After downloading has been completed and the SCO bit has been cleared to 0, FRQCR can be
changed to a desired value.
Rev. 1.00 Jun. 26, 2008 Page 1426 of 1692
REJ09B0393-0100