SH7280 Datasheet, PDF (1459/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
(2.5) The value of the DPFR parameter must be checked to confirm the download result.
A recommended procedure for confirming the download result is shown below.
1. Check the value of the DPFR parameter (one byte of start address of the download
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
2. If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
3. If the value of the DPFR parameter is different from before downloading, check the SS bit
(bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program
selection and FKEY register setting were normal, respectively.
(2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is
set to the FUBRA parameter for initialization.
1. The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
R4). The settable Iφ of the FPEFEQ parameter is 40 MHz.
When the frequency is set out of this range, an error is returned to the FPFR parameter of
the initialization program and initialization is not performed. For details on the frequency
setting, see the description in section 26.4.3 (2.1), Flash Programming/Erasing Frequency
Parameter (FPEFEQ: General Register R4 of CPU).
2. The start address in the user branch destination is set to the (FUBRA: CPU general register
R5) parameter.
When the user branch processing is not required, 0 must be set to FUBRA.
When the user branch is executed, the branch destination is executed in flash memory other
than the one that is to be programmed. The area of the on-chip program that is downloaded
cannot be set.
The program processing must be returned from the user branch processing by the RTS
instruction.
See the description in section 26.4.3 (2.2), Flash User Branch Address Setting Parameter
(FUBRA: General Register R5 of CPU).
Rev. 1.00 Jun. 26, 2008 Page 1429 of 1692
REJ09B0393-0100