SH7280 Datasheet, PDF (238/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 8 Data Transfer Controller (DTC)
Initial
Bit
Bit Name Value R/W Description
0
ERR
0
R/(W)* Transfer Stop Flag
Indicates that a DTC address error or NMI interrupt has
occurred.
If a DTC address error or NMI interrupt occurs while the
DTC is active, a DTC address error handling or NMI
interrupt handling processing is executed after the DTC
has released the bus mastership. The DTC halts after a
data transfer or a transfer information writing state
depending on the NMI input timing.
Note that a writing state is not exact, when the DTC halts
after a data transfer. When the data is transferred, set a
transfer information once again (except that a read skip is
performed).
0: No interrupt has occurred
1: An interrupt has occurred
[Clearing condition]
• When writing 0 after reading 1
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Rev. 1.00 Jun. 26, 2008 Page 208 of 1692
REJ09B0393-0100