SH7280 Datasheet, PDF (895/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 17 Serial Communication Interface with FIFO (SCIF)
Figure 17.8 shows an example of the operation for reception.
Serial
data
Start
1 _bit
0 D0
Data
Parity Stop Start
bit bit bit
D1
D7 0/1 1
0 D0
Data
Parity Stop
bit
bit
1
D1
D7
0/1 1
Idle state
(mark state)
RDF
FER
RXI interrupt
request
One frame
Data read and RDF flag
read as 1 then cleared to 0
by RXI interrupt handler
ERI interrupt request
generated by receive
error
Figure 17.8 Example of SCIF Receive Operation
(8-Bit Data, Parity, 1 Stop Bit)
Rev. 1.00 Jun. 26, 2008 Page 865 of 1692
REJ09B0393-0100