SH7280 Datasheet, PDF (1533/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 28 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
3
MSTP53 1
R/W Module Stop 53
When the MSTP53 bit is set to 1, the supply of the
clock to the SCI4 is halted.
0: SCI4 runs.
1: Clock supply to SCI4 halted.
Note: Write 1 to this bit in the SH7243.
2
MSTP52 1
R/W Module Stop 52
When the MSTP52 bit is set to 1, the supply of the
clock to the ADC1 is halted.
0: ADC1 runs.
1: Clock supply to ADC1 halted.
1
MSTP51 1
R/W Module Stop 51
When the MSTP51 bit is set to 1, the supply of the
clock to the ADC2 is halted.
0: ADC2 runs.
1: Clock supply to ADC2 halted.
Note: Write 1 to this bit in the SH7285, SH7243.
0
MSTP50 1
R/W Module Stop 50
When the MSTP50 bit is set to 1, the supply of the
clock to the SSU is halted.
0: SSU runs.
1: Clock supply to SSU halted.
Note: Write 1 to this bit in the SH7243.
28.3.6 Standby Control Register 6 (STBCR6)
STBCR6 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. STBCR6 is initialized to H'60 by a power-on reset but retains its previous value by a
manual reset or in software standby mode. Only byte access is possible.
Bit: 7
6
5
4
3
2
1
0
USB MSTP USB MSTP
SEL*¹ 66*² CLK
64




Initial value: 1
1
0
1
1
1
1
1
R/W: R/W R/W R/W R/W R
R
R
R
Rev. 1.00 Jun. 26, 2008 Page 1503 of 1692
REJ09B0393-0100