SH7280 Datasheet, PDF (15/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

9.5.11 Bus Arbitration ................................................................................................. 375
9.5.12 Others................................................................................................................ 377
Section 10 Direct Memory Access Controller (DMAC) .....................................381
10.1 Features............................................................................................................................. 381
10.2 Input/Output Pins.............................................................................................................. 383
10.3 Register Descriptions........................................................................................................ 384
10.3.1 DMA Source Address Registers (SAR)............................................................ 389
10.3.2 DMA Destination Address Registers (DAR).................................................... 390
10.3.3 DMA Transfer Count Registers (DMATCR) ................................................... 391
10.3.4 DMA Channel Control Registers (CHCR) ....................................................... 392
10.3.5 DMA Reload Source Address Registers (RSAR) ............................................. 400
10.3.6 DMA Reload Destination Address Registers (RDAR) ..................................... 401
10.3.7 DMA Reload Transfer Count Registers (RDMATCR)..................................... 402
10.3.8 DMA Operation Register (DMAOR) ............................................................... 403
10.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).............. 407
10.4 Operation .......................................................................................................................... 409
10.4.1 Transfer Flow.................................................................................................... 409
10.4.2 DMA Transfer Requests ................................................................................... 411
10.4.3 Channel Priority................................................................................................ 415
10.4.4 DMA Transfer Types........................................................................................ 418
10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing ................................ 427
10.5 Usage Notes ...................................................................................................................... 431
10.5.1 Setting of the Half-End Flag and the Half-End Interrupt.................................. 431
10.5.2 Timing of DACK and TEND Outputs .............................................................. 431
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) .....................................433
11.1 Features............................................................................................................................. 433
11.2 Input/Output Pins.............................................................................................................. 439
11.3 Register Descriptions........................................................................................................ 440
11.3.1 Timer Control Register (TCR).......................................................................... 444
11.3.2 Timer Mode Register (TMDR) ......................................................................... 448
11.3.3 Timer I/O Control Register (TIOR) .................................................................. 451
11.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) ................................ 470
11.3.5 Timer Interrupt Enable Register (TIER) ........................................................... 471
11.3.6 Timer Status Register (TSR)............................................................................. 476
11.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)............................... 483
11.3.8 Timer Input Capture Control Register (TICCR) ............................................... 485
11.3.9 Timer Synchronous Clear Register (TSYCR)................................................... 486
11.3.10 Timer A/D Converter Start Request Control Register (TADCR) ..................... 488
Rev. 1.00 Jun. 26, 2008 Page xv of xxx