SH7280 Datasheet, PDF (1359/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.2 USB Interrupt Flag Register 1 (USBIFR1)
Together with USB interrupt flag register 0 (USBIFR0), USBIFR1 indicates interrupt status
information required by the application. When an interrupt occurs, the corresponding bit is set to 1
and an interrupt request is sent to the CPU according to the combination with USB interrupt
enable register 1 (USBIER1). Clearing is performed by writing 0 to the bit to be cleared, and 1 to
the other bits. However, VBUSMN is a status bit, and cannot be cleared.
USBIFR1 is initialized to H'20 by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
VBU
SMN
EP3TR EP3TS VBUSF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W
Bit
7 to 4
Bit Name

Initial
Value
All 0
3
VBUSMN 0
2
EP3TR
0
1
EP3TS
0
0
VBUSF
0
R/W Description
R
Reserved
The write value should always be 0.
R
Status bit for monitoring the status of the VBUS pin.
The status of the VBUS pin is reflected.
0: Disconnected
1: Connected
R/W EP3 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is
received from the host. A NACK handshake is
returned to the host until data is written to the FIFO
buffer and packet transmission is enabled.
R/W EP3 Transmit Complete
This bit is set when data is transmitted to the host
from endpoint 3 and an ACK handshake is returned.
R/W UBS Disconnection Detection
This bit is set to 1 when a function is connected to or
disconnected from the USB bus. Use the VBUSCNT
pin of this module to detect connection/disconnection.
Rev. 1.00 Jun. 26, 2008 Page 1329 of 1692
REJ09B0393-0100