SH7280 Datasheet, PDF (769/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 15 Watchdog Timer (WDT)
15.3.2 Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, overflow flags, and timer enable bit.
WTCSR is initialized to H'18 by a power-on reset caused by the RES pin or in software standby
mode.
Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from
WTCSR.
Note: The method for writing to WTCSR differs from that for other registers to prevent
erroneous writes. See section 15.3.4, Notes on Register Access, for details.
Bit: 7
6
5
4
IOVF WT/IT TME
-
Initial value: 0
0
0
1
R/W: R/(W) R/W R/W R
3
2
1
0
-
CKS[2:0]
1
0
0
0
R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
IOVF
0
R/(W) Interval Timer Overflow
Indicates that WTCNT has overflowed in interval timer
mode. This flag is not set in watchdog timer mode.
0: No overflow
1: WTCNT overflow in interval timer mode
[Clearing condition]
• When 0 is written to IOVF after reading IOVF
Rev. 1.00 Jun. 26, 2008 Page 739 of 1692
REJ09B0393-0100