SH7280 Datasheet, PDF (1630/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 31 Electrical Characteristics
31.3.2 Control Signal Timing
Table 31.6 Control Signal Timing
Conditions: V_CC = PLLV_CC = 3.0 to 5.5 V, AV_CC = AVREF = 4.5 to 5.5 V,
V_SS = PLLV_SS = AVREFVSS = AV_SS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Bφ = 50 MHz
Item
Symbol Min.
Max.
Unit Figure
RES pulse width
RES setup time*¹
RES hold time
MRES pulse width
MRES setup time
MRES hold time
t
RESW
20*²

t_RESS
65

t_RESH
15

t
20
MRESW

t
MRESS
100

t
15
MRESH

t
Figures 31.4,
cyc
ns ^{31.5, 31.7,}
31.8
ns
t
cyc
ns
ns
MD1, MD0, FWE setup time
BREQ setup time
BREQ hold time
NMI setup time*¹
NMI hold time
IRQ7 to IRQ0 setup time*¹
IRQ7 to IRQ0 hold time
IRQOUT/REFOUT output delay time
BACK delay time
t
MDS
t_BREQS
t
BREQH
t_NMIS
t_NMIH
t_IRQS
t
IRQH
t
IRQOD
t
BACKD
20
—
t
cyc
1/2t_cyc + 15 
ns
1/2t + 10
cyc

ns
60

ns
10

ns
35

ns
10

ns

100
ns

1/2t + 20 ns
cyc
Figure 31.7
Figure 31.9
Figure 31.8
Figure 31.10
Figure 31.9
Bus tri-state delay time 1
t
0
BOFF1
100
ns
Bus tri-state delay time 2
t_BOFF2
0
100
ns
Bus buffer on time 1
t
0
BON1
30
ns
Bus buffer on time 2
t_BON2
0
30
ns
Notes: 1. RES, NMI, and IRQ7 to IRQ0 are asynchronous signals. When these setup times are
observed, a change of these signals is detected at the clock rising edge. If the setup
times are not observed, detection of a signal change may be delayed until the next
rising edge of the clock.
2. In standby mode, t_RESW = t_OSC1 (10 ms).
Rev. 1.00 Jun. 26, 2008 Page 1600 of 1692
REJ09B0393-0100