SH7280 Datasheet, PDF (104/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 4 Clock Pulse Generator (CPG)
USBXTAL*
USBEXTAL*
On-chip oscillator
Oscillator
Divider
×1
×1/2
×1/4
×1/8
XTAL
Crystal
oscillator
EXTAL
Oscillation stop
detection
Oscillation
stop detection
circuit
PLL circuit
(×8)
USB clock*
(Uφ :48MHz)
Internal clock
(Iφ, Max. 100 MHz)
Bus clock
(Bφ = CK, Max. 50 MHz)
Peripheral clock
(Pφ, Max. 50 MHz)
MTU2S clock
(Mφ, Max. 100 MHz)
AD clock
(Aφ, Max. 50 MHz)
CK
CPG control unit
Clock frequency
control circuit
Standby control circuit
OSCCR FRQCR MCLKCR ACLKCR STBCR STBCR2 STBCR3 STBCR4 STBCR5 STBCR6
Bus interface
[Legend]
FRQCR: Frequency control register
MCLKCR: MTU2S clock frequency control register
ACLKCR: AD clock frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
HPB bus
STBCR3: Standby control register 3
STBCR4: Standby control register 4
STBCR5: Standby control register 5
STBCR6: Standby control register 6
OSCCR: Oscillation stop detection control register
Note: * Not applied to the SH7243
Figure 4.1 Block Diagram of Clock Pulse Generator
Rev. 1.00 Jun. 26, 2008 Page 74 of 1692
REJ09B0393-0100