SH7280 Datasheet, PDF (345/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
9.5.3 Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 1, 4, 5, and 7 to insert wait cycles independently in read
access and in write access. Areas 0, 2, 3, and 6 have common access wait for read cycle and write
cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access
shown in figure 9.8.
T1
Tw
T2
Read
CK
A25 to A0
CSn
RD/WR
RD
D15 to D0
Write
WEn
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.8 Wait Timing for Normal Space Access (Software Wait Only)
Rev. 1.00 Jun. 26, 2008 Page 315 of 1692
REJ09B0393-0100