SH7280 Datasheet, PDF (1669/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 31 Electrical Characteristics
31.3.10 SCIF Module Timing
Table 31.14 SCIF Module Timing
Conditions: V_CC = 3.0 to 5.5 V, AV_CC = AVREF = 4.5 to 5.5V,
V_SS = PLLV_SS = AVREFVSS = AV_SS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol Min.
Input clock cycle (clocked synchronous) t_Scyc
6
(asynchronous)
4
Input clock rise time
Input clock fall time
Input clock width
Transmit data delay time
(clocked synchronous)
t
—
SCKr
t
—
SCKf
t
0.4
SCKW
t
—
TXD
Receive data setup time
(clocked synchronous)
t
3t + 20
RXS
pcyc
Receive data hold time
(clocked synchronous)
t_RXH
3t_pcyc + 20
Note:
t
pcyc
indicates
peripheral
clock
(Pφ)
cycle.
Max.
—
—
1.5
1.5
0.6
3t + 20
pcyc
—
—
Unit
t_pcyc
t_pcyc
t
pcyc
t
pcyc
t
Scyc
t
pcyc
ns
ns
Figure
Figure 31.47
Figure 31.47
Figure 31.47
Figure 31.47
Figure 31.47
Figure 31.48
Figure 31.48
Figure 31.48
SCK
t_SCKW
t_SCKr
t_Scyc
t_SCKf
Figure 31.47 SCK Input Clock Timing
Rev. 1.00 Jun. 26, 2008 Page 1639 of 1692
REJ09B0393-0100