SH7280 Datasheet, PDF (1715/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

General registers ....................................... 23
Global base register (GBR) ...................... 25
H
Halt mode ............................................. 1063
Hardware protection ............................. 1441
H-UDI commands................................. 1516
H-UDI interrupt ............................ 133, 1519
H-UDI related pin timing...................... 1648
H-UDI reset .......................................... 1519
I
I/O port timing ...................................... 1647
I/O ports................................................ 1273
I²C bus format......................................... 944
I²C bus interface 3 (IIC3) ....................... 925
ID Reorder ............................................ 1032
IIC3 module timing .............................. 1645
Immediate data ......................................... 32
Immediate data accessing ......................... 32
Immediate data format.............................. 29
Initial user branch processing time ....... 1447
Initial values of control registers .............. 27
Initial values of general registers .............. 27
Initial values of system registers............... 27
Initiation intervals
of user branch processing ..................... 1447
Input sampling
and A/D conversion time ........................ 997
Instruction features ................................... 30
Instruction format ..................................... 39
Instruction set ........................................... 43
Integer division instructions ................... 113
Interrupt controller (INTC)..................... 119
Interrupt exception handling................... 110
Interrupt exception handling vectors
and priorities ........................................... 137
Interrupt priority level............................. 109
Interrupt response time ........................... 149
IRQ interrupts ......................................... 134
J
Jump table base register (TBR)................. 25
L
Load-store architecture ............................. 30
Local acceptance filter mask
(LAFM)................................................. 1029
Location of transfer information
and DTC vector table .............................. 211
Logic operation instructions...................... 55
M
Mailbox................................................. 1020
Mailbox control..................................... 1020
Mailbox structure .................................. 1024
Manual reset.................................. 104, 1494
Master receive operation......................... 947
Master transmit operation ....................... 945
MCU extension mode ............................... 64
MCU operating modes .............................. 63
Message control field............................ 1025
Message data fields ............................... 1030
Message receive sequence .................... 1070
Message transmission sequence............ 1067
Micro processor interface (MPI)........... 1020
Module standby function ...................... 1512
Module standby mode setting ........ 242, 817,
................................................................ 924
MPX-I/O interface .................................. 318
MTU2 functions...................................... 434
MTU2 interrupts ..................................... 616
MTU2 output pin initialization ............... 649
MTU2, MTU2S module timing ............ 1635
Rev. 1.00 Jun. 26, 2008 Page 1685 of 1692
REJ09B0393-0100